The present invention relates to a semiconductor memory device.
FIG. 9 illustrates the structure of the memory cell peripheral circuits in a semiconductor memory device in the prior art. This semiconductor memory device includes a sense amplifier block sa, a pair of memory cell blocks mc0 and mc1, a pair of word driver blocks wd1-0 and wd1-1, a pair of decoder blocks dec 1-0 and dec 1-1 and a control circuit block cnt1.
The sense amplifier block sa, to which equalize signals EQ, EQ0 and EQ1, a sense amplifier activating signal SE and transfer signals TG0 and TG1 are input, is connected to a bit line pair BL0/BL0b and a bit line pair BL1/BL1b. The potential levels of the equalize signals EQ, EQ0 and EQ1 and the potential level of the sense amplifier activating signal SE swing back and forth between a first source potential VDD and a ground potential VSS, whereas the potential levels of the transfer signals TG0 and TG1 swing back and forth between a second source potential VPP and the ground potential VSS.
The sense amplifier block sa is constituted of a sense amplifier unit amp and a sense amplifier control circuit unit acnt.
The sense amplifier unit amp is constituted of PMOS transistors P0 and P1 and NMOS transistors N0, N1, N00, N01, N02, N03, N04, N10, N11, N12, N13 and N14.
The gate of the PMOS transistor P0 is connected to a bit line BL, the drain is connected to a bit line BLb and the source is connected to a sense node SP. The gate of the PMOS transistor P1 is connected to the bit line BLb, the drain is connected to the bit line BL and the source is connected to the sense node SP. The gate of the NMOS transistor N0 is connected to the bit line BL, the drain is connected to the bit line BLb and the source is connected to a sense node SN. The gate of the NMOS transistor N1 is connected to the bit line BLb and the drain is connected to the bit line BL and the source is connected to the sense node SN.
On/off control of the NMOS transistor N00, whose drain is connected to the bit line BL0b and whose source is connected to the bit line BLb, is implemented by using the transfer signal TG0 input to the gate. On/off control of the NMOS transistor N01, whose drain is connected to the bit line BL0 and whose source is connected to the bit line BL is implemented by using the transfer signal TG0 input to the gate.
On/off control of the NMOS transistor N10, whose drain is connected to the bit line BL1b and whose source is connected to the bit line BLb is implemented by using the transfer signal TG1 input to the gate. On/off control of the NMOS transistor N11, whose drain is connected to the bit line BL1 and whose source is connected to the bit line BL is implemented by using the transfer signal TG1 input to the gate.
On/off control of the NMOS transistor N02, whose drain is connected to the bit line BL0b and whose source is connected to a third source potential VBL (=xc2xd VDD) is implemented by using the equalize signal EQ0 input to the gate. On/off control of the NMOS transistor N03, whose drain is connected to the bit line BL0 and whose source is connected to the third source potential VBL is implemented by using the equalize signal EQ0 input to the gate. On/off control of the NMOS transistor N04, whose drain is connected to the bit line BL0b and whose source is connected to the bit line BL0 is implemented by using the equalize signal EQ0 input to the gate.
On/off control of the NMOS transistor N12, whose drain is connected to the bit line BL1b and whose source is connected to the source potential VBL is implemented by using the equalize signal EQ1 input to the gate. On/off control of the NMOS transistor N13, whose drain is connected to the bit line BL1 and whose source is connected to the third source potential VBL is implemented by using the equalize signal EQ1 input to the gate. On/off control of the NMOS transistor N14, whose drain is connected to the bit line BL1b and whose source is connected to the bit line BL1, is implemented by using the equalize signal EQ1 input to the gate.
In response to the sense amplifier activating signal SE, the sense amplifier control circuit unit acnt supplies the first source potential VDD to the sense node SP and supplies the ground potential VSS to the sense node SN. In addition, in response to the equalize signal EQ, it supplies the third sour VBL to the sense node SP and the sense node SN.
In the semiconductor memory device in the prior art illustrated in FIG. 9, the equalization (balancing of potentials) for the bit line pair BL0/BL0b and the bit line pair BL1/BL1b is achieved by supplying third source potential to the bit line pair BL0/BL0b and the bit line pair BL1/BL1b via the NMOS transistors N02, N03 and N04 and the NMOS transistors N12, N13 and N14 respectively.
However, since the gate potentials (=potentials of the equalize signals EQ0 and EQ1) at the NMOS transistors N02, N03, N04, N12, N13 and N14 during such an equalization operation are at the first source potential VDD, the voltage Vgs between the gates and the sources is at xc2xd VDD.
When operating the semiconductor memory device in the prior art with the first source potential VDD set at 1.0Vxcx9c2.0V in order to, for instance, save energy, the voltage Vgs between the gates and the sources at the NMOS transistors N02, N03, N04, N12, N13 and N14 is set within the range of 0.5Vxcx9c1.0V, which raises the concern that a sufficient margin relative to the threshold voltage Vt may not be assured. In such a case, limits are set on the currents flowing through the individual NMOS transistors N02, N03, N04, N12, N13 and N14, which makes it difficult to equalize the bit line pairs BL0/BL0b and BL1/BL1b quickly.
Likewise, when equalizing the bit line pair BL/BLb via the NMOS transistors N00, N01, N10 and N11, too, there is a concern that the length of time required for the equalization may be large since the gate potentials (=potentials of the transfer signals TG0 and TG1) of the individual NMOS transistors N00, N01, N10 and N11 during the equalization operation are set at the first source potential VDD.
In addition, while FIG. 9 illustrates a semiconductor memory device in the prior art provided with a single sense amplifier block sa, a semiconductor memory device is normally provided with a plurality of sense amplifier blocks and consequently, a plurality of memory cell blocks and a plurality of word driver blocks in correspondence. Furthermore, each sense amplifier block is provided with a great number of sense amplifiers. When the number of sense amplifiers increases in this manner, parasitic capacitance and parasitic resistance in the lines through which the equalize signals EQ0 and EQ1 are provided increase, which results in a delay occurring when the potential levels of the equalize signals EQ0 and EQ1 shift.
In the semiconductor memory device in the prior art illustrated in FIG. 9, when reading out data stored in a cell capacitor C00, for instance, it is necessary to shift the potential at a word line WL00 to the second source potential VPP after the potential of the equalize signal EQ0 shifts to the ground potential VSS and the bit line pair BL0/BL0b are completely cut off from the third source potential VBL to ensure that a read error does not occur due to the electrical charge discharged from the cell capacitor C00 discharged to the third source potential VBL via the NMOS transistors N02 and N03. However, the delay occurring in the shift of the potential levels of the equalize signals EQ0 and EQ1 described above necessitates a delay in the timing with which the potential level at the word line shifts and, consequently, the access speed of the semiconductor memory device is lowered.
An object of the present invention, which has been completed by addressing the problems discussed above, is to provide a semiconductor memory device which is capable of high speed access even when energy efficiency and larger capacity are achieved.
In order to achieve the object described above, the present invention provides a semiconductor memory device comprising one or more memory elements that store information, a bit line pair through which information read out from a memory element is transmitted, a means for amplification that amplifies the potentials at one bit line and the other bit line constituting the bit line pair to a reference potential and a first source potential respectively and a means for equalization that is controlled by an equalize signal achieving a second source potential which is higher than the first source potential and equalizes the potentials at the bit line pair to a third source potential.
By assuring a sufficient difference between the second source potential and the first source potential, it is possible to equalize the bit line pair quickly and with a high degree of reliability even when the first source potential is set at a low level in order to, for instance, achieve energy efficiency and the like.
In addition, it is desirable to provide the means for equalization with a first potential supply transistor that supplies the third source potential to one bit line, a second potential supply transistor that supplies the third source potential to the other bit line and a connector transistor that connects the one bit line to the other bit line, and to input the equalize signal to the gates of the first potential supply transistor, the second potential supply transistor and the connector transistor.
When each transistor is constituted of, for instance, an NMOS transistor by setting the second source potential equal to or greater than the sum of the threshold voltage at these transistors and the first source potential, the gate voltage for turning on the individual transistors can be set equal to or greater than the threshold voltage with a high degree of reliability. Consequently, the ON resistance at the individual transistors that is controlled by the equalize signal can be kept at a low level.
Alternatively, one bit line may be connected to the means for amplification via a first amplification means connector transistor with the other bit line connected to the means for amplification via a second amplification means connector transistor. In this case, the first amplification means connector transistor and the second amplification means connector transistor are controlled with an amplification means connector transistor control signal achieving the second source potential.
When each transistor is constituted of, for instance, an NMOS transistor by setting the second source potential equal to or greater than the sum of the threshold voltage at these transistors and the first source potential, the gate voltage for tuning on the individual transistors can be set equal to or greater than the threshold voltage with a high degree of reliability. Consequently, the ON resistance at the individual transistor that is controlled by the amplification means connector transistor control signal can be kept at a low level when amplifying the potentials at the bit line pair.
In addition, according to the present invention, a semiconductor memory device comprising a first memory element group constituted of one or more memory elements that store information, a second memory element group constituted of one or more memory elements that store information, a first bit line pair through which information read out from one or more memory elements in the first memory element group is transmitted, a second bit line pair through which information read out from one or more memory elements in the second memory element group is transmitted, a means for amplification that amplifies the potentials at one bit line and the other bit line constituting the first bit line pair to a reference potential and a first source potential respectively and amplifies the potentials at one bit line and the other bit line constituting the second bit line pair to the reference potential and the first source potential respectively, a first means for equalization that is controlled by a first control signal achieving a second source potential higher than the first source potential and equalizes the first bit line pair to a third source potential and a second means for equalization that is controlled by a second control signal achieving the second source potential and equalizes the second bit line pair to the third source potential.
By assuring a sufficient difference between the second source potential and the first source potential, equalization of the first bit line pair and the second bit line pair can be achieved quickly and with a high degree of reliability even when the first source potential is set at a low level to achieve, for instance, energy efficiency and the like.
The semiconductor memory device may assume a structure in which one bit line in the first bit line pair is connected to the means for amplification via a first amplification means connector transistor, the other bit line in the first bit line pair is connected to the means for amplification via a second amplification means connector transistor, one bit line in the second bit line pair is connected to the means for amplification via a third amplification means connector transistor and the other bit line in the second bit line pair is connected to the means for amplification via a fourth amplification means connector transistor. In this case, the first amplification means connector transistor and the second amplification means connector transistor are controlled by a second control signal and the third amplification means connector transistor and the fourth amplification means connector transistor are controlled by a first control signal.
When each transistor is constituted of, for instance, an NMOS transistor in this structure, by setting the second source potential equal to or greater than the sum of the threshold voltage and the first source potential at the transistors, the gate voltage for turning on the individual transistors can be set equal to or greater than the threshold voltage with a high degree of reliability. Thus, it becomes possible to keep the ON resistance at the first amplification means connector transistor and the second amplification means connector transistor that are controlled by the second control signal when amplifying the potentials at the first bit line pair at a low level, and to keep the ON resistance at the third amplification means connector transistor and the fourth amplification means connector transistor that are controlled by the first control signal when amplifying the potentials at the second bit line pair at a low level.
Furthermore, the first means for equalization and the third and fourth amplification means connector transistors are commonly controlled by the first control signal and the second means for equalization and the first and second amplification means connector transistors are commonly controlled by the second control signal, to achieve simplification of the circuit in the semiconductor memory device.
It is desirable to provide a plurality of first word lines connected to the individual memory elements in the first memory element group, a first means for word line drive that selectively drives one of the plurality of first word lines in correspondence to the potential level of the first control signal, a plurality of second word lines connected to the individual memory elements in the second memory element group and a second means for word line drive that selectively drives one of the plurality of the second word lines in correspondence to the potential level of the second control signal.
By adopting this structure, it becomes possible to set the timing with which the first word line is driven in synchronization with the shift of the potential level of the first control signal. It also becomes possible to set the timing with which the second word line is driven in synchronization with the shift of the potential of the second control signal.
It is desirable to provide the first means for word line drive with a plurality of first word line drive units that individually drive the plurality of first word lines and a first selection unit that selects one of the plurality of first word line drive units in correspondence to the potential level of the first control signal and the potential level of an address signal. In addition, it is desirable to provide the second means for word line drive with a plurality of second word line drive units that individually drive the plurality of second word lines and a second selection unit that selects one of the plurality of second word line drive units in correspondence to the potential level of the second control signal and the potential level of the address signal.
In this structure, the first selection unit provided at the first means for word line drive and the second selection unit provided at the second means for word line drive are controlled by the common address signal. As a result, further simplification of the circuit structure in the semiconductor memory device is achieved.